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Department of Computer Science
The George Washington University 801 22nd Street NW, Suite 704 Washington DC 20052 Voice: (202) 994-7181 Fax: (202) 994-4875 E-mail: cs@gwu.edu Seminar/talk SummaryTitleCombinatorial Architecture: A Multi-core Processor Running on Regular Sequential Code Date2009-11-12 4:00 pm SpeakerSimon Berkovich, Ph.D., GWU PlaceRoom 736 Academic Center, CS Conference Room ContentThis talk presents an innovative computer architecture based on combinatorial interconnections of processor and memory resources. These interconnections are arranged in accordance with the so-called Balanced Incomplete Block Designs (BIBD). The exchange of information is performed by means of direct interaction of replicated objects rather than by traditional shipping of data from a source to a destination. The system automatically partitions sequential programs into concurrent streams and effectively brings in processing and routing capabilities. Hardware is built of well- developed types of components without complicated functional interactions, like synchronization, branch scheduling, and pipeline hazards. Software is the same as for conventional serial computers. With this architecture it is possible to enjoy a universal speedup by factor of 3 and more without any particular efforts just by virtue of the unusual interconnections of the operative components. The redundancy due to replication of functional elements may be exploited for the purpose of fault-tolerance. The system is flexible in trading the speedup for energy saving. DetailAttachment:Simon Berkovich CS Colloquium.pdf Back |
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